An Efficient Spectral Leakage Filtering for IEEE 802.11af in TV White Space

Orthogonal frequency division multiplexing (OFDM) has been widely adopted for modern wireless standards and become a key enabling technology for cognitive radios. However, one of its main drawbacks is significant spectral leakage due to the accumulation of multiple sinc-shaped subcarriers. In this paper, we present a novel pulse shaping scheme for efficient spectral leakage suppression in OFDM based physical layer of IEEE 802.11af standard. With conventional pulse shaping filters such as a raised-cosine filter, vestigial symmetry can be used to reduce spectral leakage very effectively. However, these pulse shaping filters require long guard interval, i.e., cyclic prefix in an OFDM system, to avoid inter-symbol interference (ISI), resulting in a loss of spectral efficiency. The proposed pulse shaping method based on asymmetric pulse shaping achieves better spectral leakage suppression and decreases ISI caused by filtering as compared to conventional pulse shaping filters

CIDPro: Custom Instructions for Dynamic Program Diversification

Timing side-channel attacks pose a major threat to embedded systems due to their ease of accessibility. We propose CIDPro, a framework that relies on dynamic program diversification to mitigate timing side-channel leakage. The proposed framework integrates the widely used LLVM compiler infrastructure and the increasingly popular RISC-V FPGA soft-processor. The compiler automatically generates custom instructions in the security critical segments of the program, and the instructions execute on the RISC-V custom co-processor to produce diversified timing characteristics on each execution instance. CIDPro has been implemented on the Zynq7000 XC7Z020 FPGA device to study the performance overhead and security tradeoffs. Experimental results show that our solution can achieve 80% and 86% timing side-channel capacity reduction for two benchmarks with an acceptable performance overhead compared to existing solutions. In addition, the proposed method incurs only a negligible hardware area overhead of 1% slices of the entire RISC-V system

A Hardware-Efficient Synchronization in L-DACS1 for Aeronautical Communications

L-band digital aeronautical communication system type-1 (L-DACS1) is an emerging standard that aims at enhancing air traffic management by transitioning the traditional analog aeronautical communication systems to the superior and highly efficient digital domain. L-DACS1 employs modern and efficient orthogonal frequency-division multiplexing (OFDM) modulation technique to achieve more efficient and higher data rate in comparison to the existing aeronautical communication systems. However, the performance of OFDM systems is very sensitive to synchronization errors such as symbol timing offset (STO) and carrier frequency offset (CFO). STO and CFO estimations are extremely important for maintaining orthogonality among the subcarriers for the retrieval of information. This paper proposes a novel efficient hardware synchronizer for L-DACS1 systems that offers robust performance at low power and low hardware resource usage. Monte Carlo simulations show that the proposed synchronization algorithm provides accurate STO estimation as well as fractional CFO estimation. Implementation of the proposed synchronizer on a widely used field-programmable gate array (FPGA) (Xilinx xc7z020clg484-1) results in a very low hardware usage which consumed 6.5%, 3.7%, and 6.4% of the total number of lookup tables, flip-flops, and digital signal processing blocks, respectively. The dynamic power of the proposed synchronizer is below 1 mW.Comment: arXiv admin note: substantial text overlap with arXiv:1801.0590

XDIVINSA: eXtended DIVersifying INStruction Agent to Mitigate Power Side-Channel Leakage

Side-channel analysis (SCA) attacks pose a major threat to embedded systems due to their ease of accessibility. Realising SCA resilient cryptographic algorithms on embedded systems under tight intrinsic constraints, such as low area cost, limited computational ability, etc., is extremely challenging and often not possible. We propose a seamless and effective approach to realise a generic countermeasure against SCA attacks. XDIVINSA, an extended diversifying instruction agent, is introduced to realise the countermeasure at the microarchitecture level based on the combining concept of diversified instruction set extension (ISE) and hardware diversification. XDIVINSA is developed as a lightweight co-processor that is tightly coupled with a RISC-V processor. The proposed method can be applied to various algorithms without the need for software developers to undertake substantial design efforts hardening their implementations against SCA. XDIVINSA has been implemented on the SASEBO G-III board which hosts a Kintex-7 XC7K160T FPGA device for SCA mitigation evaluation. Experimental results based on non-specific t-statistic tests show that our solution can achieve leakage mitigation on the power side channel of different cryptographic kernels, i.e., Speck, ChaCha20, AES, and RSA with an acceptable performance overhead compared to existing countermeasures.This work has been supported in part by EPSRC via grant EP/R012288/1, under the RISE (http://www.ukrise.org) programme.Peer ReviewedPostprint (author's final draft

Efficient Integer Frequency Offset Estimation Architecture for Enhanced OFDM Synchronization

An integer frequency offset (IFO), in orthogonal frequency-division multiplexing (OFDM) systems, causes a circular shift of the sub-carrier indices in the frequency domain.IFO can be mitigated through strict RF front-end design but this is challenging and expensive. Therefore, IFO is estimated and removed at baseband, allowing the RF front-end specification to be relaxed, thus reducing system cost. For applications susceptible to Doppler shift, and multi-standard radios requiring wide frequency range access, careful RF design may be insufficient without IFO estimation. This paper proposes a novel approach for IFO estimation with reduced power consumption and computational cost. A four-fold resource sharing architecture reduces computational cost, while a multiplierless technique and carefully optimised wordlengths yield further power reduction while maintaining a good accuracy. The novel method is shown to achieve excellent performance, similar to the theoretically achievable bound. In fact, performance is significantly better than conventional techniques, while being much more efficient. When implemented for IEEE 802.16-2009, the proposed method saves 78% power over the conventional technique on low-power FPGA devices. The method is applicable to IEEE 802.11 and IEEE 802.22

Risk Management at Military Commercial Joint Stock Bank in Vietnam

This research is conducted for examining the framework for risk management in the Basel II accord, the Basel II risk management model at the Military Commercial Joint Stock Bank. Data were collected from annual reports for the period from 2015 to 2017 of the Military Commercial Joint Stock Bank. The results show that the implementation of risk management under Basel II at Military Bank still faces many difficulties in the pressure of capital increase, database system, human resource quality, and cost of implementation. The study suggest some solutions for Military Bank to implement successfully Basel II, emphasizing the role of human resource quality, modernizing the data system and the specific mechanism for raising capital. The results of this research is a reference for Vietnamese commercial banks in identifying, controlling and responding various risks in banking activities in the context of Vietnam. Keywords: Basel II, Risk management, Military Bank DOI: 10.7176/RJFA/10-12-06 Publication date:June 30th 201

Challenges in Employing BASEL II at Military Commercial Joint Stock Bank

This paper is conducted for examining the framework for risk management in the Basel II accord, the Basel II risk management model at the Military Commercial Joint Stock Bank. Data were collected from annual reports for the period from 2015 to 2017 of the Military Commercial Joint Stock Bank. The results show that the implementation of risk management under Basel II at Military Bank still faces many difficulties in the pressure of capital increase, database system, human resource quality, and cost of implementation. The study suggests some solutions for Military Bank to implement successfully Basel II, emphasizing the role of human resource quality, modernizing the data system and the specific mechanism for raising capital. The results of this research is a reference for Vietnamese commercial banks in identifying, controlling and responding various risks in banking activities in the context of Vietnam in particular and in emerging countries in general. Keywords: Basel II, Risk management, Military Ban